The ttl data book for design engineers pdf

Register now and create a free account to access unlimited books, fast download, ad-free and books in good quality! This best selling book has become the standard reference to TTL devices. It tells what they are, how they work, and how to use them. TTL Cookbook is filled with typical circuits and practical applications to aid the user who wants to learn about and use TTL.

Book jacket. Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible.

The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his ""tools"" — or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptions of actual design exercises. The first of these is a fairly simple exercise in CMOS design; the second is a much more complex design for an electronic game, using TTL devices.

Part 3 focuses on microprocessors. Today, surface-mounted CMOS versions of the series are used in various applications in electronics and for glue logic in computers and industrial electronics. They are useful for rapid breadboard -prototyping and for education and remain available from most manufacturers. The fastest types and very low voltage versions are typically surface-mount only, however. Additional characters in a part number identify the package and other variations.

Unlike the older resistor-transistor logic integrated circuits, bipolar TTL gates were unsuitable to be used as analog devices, providing low gain, poor stability, and low input impedance.

Inverting gates could be cascaded as a ring oscillator , useful for purposes where high stability was not required. Although the series was the first de facto industry standard TTL logic family i. The quad NAND gate was the first product in the series, introduced by Texas Instruments in a military grade metal flat package W in October The pin assignment of this early series differed from the de facto standard set by the later series in DIP packages in particular, ground was connected to pin 11 and the power supply to pin 4, compared to pins 7 and 14 for DIP packages.

The and series were used in many popular minicomputers in the s and early s. In , typical quantity-one pricing for the SN military grade, in ceramic welded flat-pack was around 22 USD. Originally the bipolar circuits provided higher speed but consumed more power than the competing series of CMOS devices.

Milspec -rated devices for use in extended temperature conditions are available as the series. Texas Instruments also manufactured radiation-hardened devices with the prefix RSN , and the company offered beam-lead bare dies for integration into hybrid circuits with a BL prefix designation.

While companies such as Mullard listed series compatible parts in data sheets, [21] by there was no mention of the family in the Texas Instruments TTL Data Book. Some companies have also offered industrial extended temperature range variants using the regular series part numbers with a prefix or suffix to indicate the temperature grade. As integrated circuits in the series were made in different technologies, usually compatibility was retained with the original TTL logic levels and power supply voltages.

Over 40 different logic subfamilies use this standardized part number scheme. TTL has the input high level above 2. The 74H family is the same basic design as the family with resistor values reduced. The 74H family provided a number of unique devices for CPU designs in the s. Many designers of military and aerospace equipment used this family over a long period and as they need exact replacements, this family is still produced by Lansdale Semiconductor.

The 74S family, using Schottky circuitry, uses more power than the 74, but is faster. The 74LS family of ICs is a lower-power version of the 74S family, with slightly higher speed but lower power dissipation than the original 74 family; it became the most popular variant once it was widely available. Many 74LS ICs can be found in microcomputers and digital consumer electronics manufactured in the s and early s. The 74F family was introduced by Fairchild Semiconductor and adopted by other manufacturers; it is faster than the 74, 74LS and 74S families.

Through the late s and s newer versions of this [ which? Part number schemes varied by manufacturer. The part numbers for series logic devices often use the following designators:.

For example, "SNN" signifies that the part is a series IC probably manufactured by Texas Instruments "SN" originally meaning "Semiconductor Network" [34] using commercial processing, is of the military temperature rating "54" , and is of the TTL family absence of a family designator , its function being the quad 2-input NAND gate "00" implemented in a plastic through-hole DIP package "N". Many logic families maintain a consistent use of the device numbers as an aid to designers.

Often a part from a different 74x00 subfamily could be substituted " drop-in replacement " in a circuit, with the same function and pin-out yet more appropriate characteristics for an application perhaps speed or power consumption , which was a large part of the appeal of the 74C00 series over the competing CDB series, for example.

But there are a few exceptions where incompatibilities mainly in pin-out across the subfamilies occurred, such as:. Wayne, Inwood Or. IN Suite J F: Km Buenos Aires. PO Box North Ryde. South Melbourne. H: Rennweg Raket- straat. Rue De La Fusee L Bat A. Place de Bretange. MD MN NJ Suite E. East Syr- acuse. NY Box Woodlawn Rd. NC Residence LAutay. Frankfurter Allee Germany; ; Haggertystrasse 1.

Asian House. Hennessy Rd.. Hong Kong. Cologno Monzese. Japan Kwang Poong Bldg.. Skelly Dr. OK Beaverton Hwy.. OR Box 2. TX VA E Bldg 6. Canada H4S1R7. Industrial Vallejo. Mexico City Laan Van de Helende Meesters A. Oslo 6. FrederiCO Ulrich. Singapore 1. Republic of Singapore. Fack S 54 Stock- holm Fu Shing Bldg.. England MKPU. TI cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.

Information on radiation- hardened and beam-lead circuits has not been included in this book, but TI has a broad line of these devices, and information is available upon request.

The indexes are designed for ease of circuit selection with margin tabs to guide you quickly to general circuit catagories, and the alphanumeric and functional indexes will let you locate specific circuit types quickly.

In addition, a section showing pin assignments, package availability, and a brief description of the circuit type arranged in type-number order is included for quick reference. Whenever practical, the MSI functions are arranged in sequence by type number to further simplify the task of locating a particular function. Another section is devoted to JAN IC's and provides a table of recom- mended usage and cross-references from TI type number to slash sheet and slash sheet to T I type number.

Another handy reference for the design engineer is the section on IC sockets and inter- connection panels from TI. Box , MS , Dallas, Texas Patent Number 3,, I Contact the factory for availability. For more information on these devices contact the factory. Essential characteristics of similar or like functions are grouped for comparative analysis, and the electrical specifications are referenced by page number.

PositiveAND gates with totem-pole outputs. PositiveAND gates with open-collector outputs Buffer and interface gates with open-collector outputs. Gates, buffers, drivers and bus transceivers with 3state outputs Positive-OR gates with totem-pole outputs..

Dual j-K edge-triggered flip-flops Single JK edgetriggered flip-flops Pulse-triggered dual flip-flops. Pulsetriggered single flip-flops.. S-R latches. Current-sensing gates. Monostable multivibrators with Schmitt-trigger inputs Retriggerable monostable multivibrators Clock generator circuits. Accumulators, arithmetic logic units, look-ahead carry generators Multipliers. Other arithmetic operators Quad,hex, and octal flip-flops Register files. Shift registers.

Other registers Latches Clock generator circuits Code converters. Bus transceivers and drivers Asynchronous counters ripple clock -negative-edge triggered Synchronous counters-Positive-edge triggered Bipolar bit-slice processor elements First-in first-out memories FI FO's.

Programmable-read-only memories PROM's Microprocessor controllers and support functions Error detection and correction circuits. W SN74S09 J. BV N 3-State 4 ns 14 ns. N 3-State 24 ns 19 ns 9. N X 8 3-State 45 ns 15 ns 0. W SN J. TI makes no warranty as to the information furnished and buyer assumes all risk in the use thereof. No liability is assumed for damages resulting from the use of the information contained in this list.

Recommendation for New Designs lists devices performing a similar sometimes identical function. Most are pin-for-pin equivalents for the competitor's part. However, the recommended part may have different pin-outs or organizations, as later technologies are listed in some cases to ensure that current high-performance components are recommended.

Only the basic circuit numbers are cross referenced. As the pin-out sometimes varies between a flat-package part and the equivalent DIP part, it is recommended that the manufacturer's specifications be consulted prior to specifying a direct replacement. Other than parts offered only in a flat package, the dual-in-line pin-outs were used as a guide in preparing the following cross references. For a complete listing of P:lrts in the 54 and 74 families, see the functional index, pages through Note: This parameter is usually specified for open-collector outputs intended to drive devices other than logic circuits.

Current out of a terminal is given as a negative value. NOTES: 1. The hold time is the actual time between two events and may be insufficient to accomplish the intended result. A minimum value is specified that is the shortest interval for which correct operation of the logic element is guaranteed. The hold time may have a negative value in which case the minimum limit defines the longest interval between the release of data and the active transition for which correct operation of the logic element is guaranteed.

Output enable time of a threestate output to high or low level, tPzx t The propagation delay time between the specified reference points on the input and output voltage waveforms with the threestate output changing from a highimpedance off state to either of the defined active levels high or low. Output disable time of a output from high or low level, tPxz t The propagation delay time between the specified reference points on the input and output voltage waveforms with the threestate output changing from either of the defined active levels high or low to a highimpedance off state.

Propagation Time Propagation delay time, tPD The time between the specified reference points on the input and output voltage waveforms with the output changing from one defined level high or low to the other defined level. Propagation delay time, lowtohigh-Ievel output, tPLH The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level.

Propagation delay time, hightolowlevel output, tpHL The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined high level to the defined low level.

Recovery Time Sense recovery time, tSR The time interval needed to switch a memory from a write mode to a read mode and to obtain valid data signals at the output. Release Time Release time, trelease The time interval between the release from a specified input terminal of data intended to be recognized and the occurrence of an active transition at another specified input terminal. Note: When specified, the interval designated "release time" falls within the setup interval and constitutes, in effect, a negative hold time.

Setup Time Setup time, tsu The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal. The setup time is the actual time between two events and may be insufficient to accomplish the setup.

The setup time may have a negative value in which case the minimum limit defines the longest interval between the active transition and the application of the other signal for which correct operation of the logic element is guaranteed. Transition Time Transition time, low-to-high-Ievel, tTLH The time between a specified low-level voltage and a specified high-level voltage on a waveform that is changing from the defined low level to the defined high level.

Transition time, highto-Iow-Ievel, tTHL The time between a specified high-level voltage and a specified low-level voltage on a waveform that is changing from the defined high level to the defined low level.

NOTE: A minimum is specified that is the least positive value of high-level input voltage for which operation of the logic element within specification limits is guaranteed.

High-level output voltage, VOH The voltage at an output terminal with input conditions applied that according to the product specification will establish a high level at the output. Input clamp voltage, VIK An input voltage in a region of relatively low differential resistance that serves to limit the input voltage swing. Low-level input voltage, VIL An input voltage level within the less positive more negative of the two ranges of values used to represent the binary variables.

NOTE: A maximum is specified that is the most positive value of low-level input voltage for which operation of the logic element within specification limits is guaranteed.

Low-level output voltage, VOL The voltage at an output terminal with input conditions applied that according to the product specification will establish a low level at the output.

Off-state output voltage, Va off The voltage at an output terminal with input conditions applied that according to the product specification will cause the output switching element to be in the off state. Note: This characteristic is usually specified only for outputs not having internal pullup elements.

On-state output voltage, VO on The voltage at an output terminal with input conditions applied that according to the product specification will cause the output switching element to be in the on state.

The number of gate equivalent circuits is that number of individual logic gates that would have to be interconnected to perform the same function. Large-Scale Integration, LSI A concept whereby a complete major subsystem or system function is fabricated as a single microcircuit. In this context a major subsystem or system, whether digital or linear, is considered to be one that contains or more equivalent gates or circuitry of similar complexity.

Medium-Scale Integration, MSI A concept whereby a' complete subsystem or system function is fabricated as a single microcircuit. The subsystem or system is smaller than for LSI, but whether digital or linear, is considered to be one that contains 12 or more equivalent gates or circuitry of similar complexity. In this context, a system, whether digital or linear, is considered to be one that contains or more gates or circuitry of similar complexity. Unless otherwise indicated, input transitions in the opposite direction to those shown have no effect at the output.

If the output is shown as a pulse, n or LS, the pulse follows the indicated input transition and persists for an interval dependent on the circuit.

These embody most of the symbols used in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register, e. In the following lines, clear is inactive high and so has no effect. The second line shows that so long as the clock input remains low while clear is high. Since on other lines of the table only the rising transition of the clock is shown to be active, the second line implicitly shows that no further change in the outputs will occur while the clock remains high or on the high-to-Iow transition of the clock.

The third line of the table represents synchronous parallel loading of the register and says that if 51 and 50 are both high then, without regard to the serial input, the data entered at A will be at output OA, data entered at B will be at OS, and so forth, following a low-to-high clock transition. The fourth and fifth lines represent the loading of high- and lowlevel data, respectively, from the shift-right serial input and the shifting of previously entered data one bit; data previously at OA is now at OS, the previous levels of Os and Oc are now at Oc and OD respectively, and the data previously at OD is no longer in the register.

This entry of serial data and shift takes place on the low-to-high transition of the clock when 51 is low and 50 is high and the levels at inputs A through D have no effect. The sixth and seventh lines represent the loading of high- and low-level data, respectively, from the shift-left serial input and the shifting of previously entered data one bit; data previously at Os is now at OA, the previous levels of Oc and 0D are now at Os and OC, respectively, and the data previously at OA is no longer in the register.

This entry of serial data and shift takes place on the low-to-high transition of the clock when 51 is high and 50 is low and the levels at inputs A through D have no effect. CL includes probe and jig capacitance. All diodes are lN or lN Waveform 1 is for an output with internal conditions such that the output Is low except whEin disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.

When measuring propagation delay times of 3-state outputs, switches Sl and S2 are closed. All diodes are 1 N or 1 N C1 30 pFf is used for testing Series 54LL devices only.

Jt'L '" 1. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

In the examples above, the phase relationships between and outputs have been chosen arbitrarily. The availability of a circuit function in a particular package is denoted by an alphabetical reference above the pin-connection diagram s.

These alphabetical references refer to mechanical outline drawings shown in this section. Factory orders for circuits described in this catalog should include a four-part type number as explained in the following example.

Instructions Dash No. Unless a specific method of shipment is specified by the customer With pos- sible additional posts , circuits will be shipped in the most practical carrier. Please contact your TI sales representative for the method that will best suit your particular needs.

Hermetic sealing is accomplished with glass. The packages are intended for insertion in mounting-hole rows on 0. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in the board during soldering. Tin-plated "bright-dipped" leads require no additional cleaning or processing when used in soldered assembly.

All other dimensions apply without modification. D1S 0. All dimensions are shown in inches and parenthetically In millimeters for reference only. Inch dimensions govern. Each pin centerline is located within 0. The compound will withstand soldering temperature with no deforma- tion and circuit performance characteristics remain stable when operated in high-humidity conditions. The packages are intended for insertion in mounting hole rows on 0.

Leads require no addi- tional cleaning or processing when used in soldered assembly. ISee Not. Q1B 0. P, ISee Not.. Inch dimensions govern, b. Each pin centerline Is located within 0. This dimension does not apply for solder-dlpped leads. When solder-dlpped leads are specified, dipped area of the lead extends from the lead tip to at least 0. Inch dimen sions govern. This dimension dt es not apply for solder-dipped leads, d.

When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0. TEXAS 0. Approximate weight is 0. Q,38jt ". All dimensions are shown in inches and parenthet- ically in millimeters for reference only.

Inch dimen- sions govern: b. Lead centerlines are located within 0. This is measured along lines located within 0.

Not applicable in Mach-Pak carrier. Index tab on pin 1 denotes orientation of package. This dimension does not apply for solder-dipped leads. When solder-dlpped leads are specified, dipped area of the lead extends from the lead tip to within 0. Solder-dipped leads are also available.

Formed leads are available to facilitate planar mount- ing of networks on flat circuit boards. Circuits can be removed from Mach-Pak carriers with lead lengths up to 0. Dimensions are shown in inches and parenthet- ically in millimeters for reference only.

Inch dimen- sions govern. Measured from centerline of outside leads. Measured from center of lead to bottom of package where lead emerges from body.

When solder-dipped leads are specified dipped area of lead extends from load tip to outside bend min- imum. Tinplated "brightdipped" leads require no additional cleaning or processing when used in soldered assembly. All dimensions are shown in inches and parenthetically in millimeters for reference only. Index point is provided on cap for terminal identification only.

Leads are within 0. This dimension determines a zone within which all body and lead irregularities lie. End configuration of pin package is at the option of TI. These product lines offer the digital systems designer a full spectrum of performance ranges in order to optimize system cost and perfor- mance. The available choices range from the very high performance of the Schottky-clamped t functions for systems operating typically up to megahertz to low-power functions with power consumption of only one milliwatt per gate.

Voltaae values, unless otherwise noted, are with respect to network ground terminal. This is the voltage between two emitters of a multiple-emitter transistor. Ratings for MSI parts are given on the individual date sheets. This eliminates the distributed capacitance associated with the floating input, bond wire, and package lead, and ensures that no degradation will occur in the propagation delay times. Some possible ways of handling unused inputs are: a. Connect unused inputs to an independent supply voltage.

Preferably, this voltage should be between VOH min and 4. Connect unused inputs to a used input if maximum drive capability of the driving output will not be exceeded. Each additional input presents a full load to the driving output at a high-level voltage but adds no loading at a low-level voltage. Connect unused inputs to VCC through a l-kD. One to 25 unused inputs may be connected to each l-kD.

Connect unused inputs to any fixed-high-Ievel compatible output such as the output of an inverter or NAND gate that has its input s grounded. Maximum high-level drive capability of the output should not be exceeded. The table below shows maximum input current requirements and nominal base resistor values for standard loads in each TTL series.